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    Author(s): Thomas H. Drayer; William E. King; Philip A. Araman; Joseph G. Tront; Richard W. Conners
    Date: 1995
    Source: Proceedings, IEEE 21st International Conference on Industrial Electronics, Control, and Instrumentation. 1284-1289.
    Publication Series: Miscellaneous Publication
    PDF: View PDF  (186 KB)

    Description

    In this paper, we investigate the use of multiple Field Programmable Gate Array (FPGA) architectures for real-time machine vision processing. The use of FPGAs for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. A common input/output interface is created for use in each of the modules, allowing interconnection of several image processing modules in a parallel or pipelined manner. This new synchronous, unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image. A method is developed to partition and compile the design into the hardware resources of multiple FPGA chips. Experimental results verify the efficiency of using common multiple FPGA architectures to implement real-time machine vision processing.

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    Citation

    Drayer, Thomas H.; King, William E., IV; Araman, Philip A.; Tront, Joseph G.; Conners, Richard W. 1995. Using Multiple FPGA Architectures for Real-time Processing of Low-level Machine Vision Functions. Proceedings, IEEE 21st International Conference on Industrial Electronics, Control, and Instrumentation. 1284-1289.

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